XC4VLX100-11FF1148C Datasheet, PDF (27/58 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
Table 33: OLOGIC Switching Characteristics
Symbol
Setup/Hold
T_ODCK / T_OCKD
Description
D1/D2 pins Setup/Hold with respect to CLK
T_OOCECK / T_OCKOCE OCE pin Setup/Hold with respect to CLK
T_OSRCK / T_OCKSR
SR/REV pin Setup/Hold with respect to CLK
T_OTCK / T_OCKT
T1/T2 pins Setup/Hold with respect to CLK
T_OTCECK / T_OCKTCE TCE pin Setup/Hold with respect to CLK
Combinatorial
T_ODQ
T_OTQ
Sequential Delays
T_IOSRON
T_OCKQ
T_RQ
T_GSRQ
Set/Reset
D1 to OQ out
T1 to TQ out
REV pin to TQ out
CLK to OQ/TQ out
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
T_RPW
Minimum Pulse Width, SR/REV inputs
Speed Grade
-12
-11
-10
Units
0.52
–0.22
0.62
–0.22
0.75
–0.22
ns
0.53
–0.33
0.64
–0.33
0.77
–0.33
ns
0.99
–0.55
1.18
–0.55
1.42
–0.55
ns
0.52
–0.22
0.62
–0.22
0.75
–0.22
ns
0.53
–0.33
0.64
–0.33
0.77
–0.33
ns
0.56
0.65
0.76
ns
0.56
0.65
0.76
ns
1.14
1.37
1.64
ns
0.41
0.49
0.59
ns
1.14
1.37
1.64
ns
1.54
1.73
2.03
ns
0.53
0.59
0.70
ns,
Min
DS302 (v3.7) September 9, 2009
www.xilinx.com
Product Specification
27