W632GU8KB Datasheet, PDF (99/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.4 Input and Output Leakage Currents
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
NOTES
Input Leakage Current
IIL
(0V ≤ VIN ≤ VDD)
-2
2
µA
1
Output Leakage Current
IOL
(Output disabled, 0V ≤ VOUT ≤ VDDQ)
-5
5
µA
2
Notes:
1. All other balls not under test = 0 V.
2. All DQ, DQS and DQS# are in high-impedance mode.
10.5 Interface Test Conditions
Figure 88 represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of
the actual load presented by a production tester. System designers should use IBIS or other
simulation tools to correlate the timing reference load to a system environment. Manufacturers
correlate to their production test conditions, generally one or more coaxial transmission lines
terminated at the tester electronics.
VDDQ
CK, CK#
DUT
DQ
DQS
DQS#
VTT = VDDQ/2
25Ω
Timing reference point
Figure 88 – Reference Load for AC Timings and Output Slew Rates
The Timing Reference Points are the idealized input and output nodes / terminals on the outside of the
packaged SDRAM device as they would appear in a schematic or an IBIS model.
The output timing reference voltage level for single ended signals is the cross point with VTT.
The output timing reference voltage level for differential signals is the cross point of the true (e.g.
DQS) and the complement (e.g. DQS#) signal.
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Publication Release Date: Jan. 20, 2015
Revision: A05