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W632GU8KB Datasheet, PDF (1/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM
W632GU8KB
32M  8 BANKS  8 BIT DDR3L SDRAM
Table of Contents-
1.
GENERAL DESCRIPTION ...................................................................................................................5
2.
FEATURES ...........................................................................................................................................5
3.
ORDER INFORMATION .......................................................................................................................6
4.
KEY PARAMETERS .............................................................................................................................7
5.
BALL CONFIGURATION ......................................................................................................................8
6.
BALL DESCRIPTION............................................................................................................................9
7.
BLOCK DIAGRAM ..............................................................................................................................11
8.
FUNCTIONAL DESCRIPTION............................................................................................................12
8.1 Basic Functionality ..............................................................................................................................12
8.2 RESET and Initialization Procedure ....................................................................................................12
8.2.1
Power-up Initialization Sequence .....................................................................................12
8.2.2
Reset Initialization with Stable Power ..............................................................................14
8.3 Programming the Mode Registers.......................................................................................................15
8.3.1
Mode Register MR0 .........................................................................................................17
8.3.1.1
Burst Length, Type and Order ................................................................................17
8.3.1.2
CAS Latency...........................................................................................................18
8.3.1.3
Test Mode...............................................................................................................18
8.3.1.4
DLL Reset...............................................................................................................18
8.3.1.5
Write Recovery .......................................................................................................19
8.3.1.6
Precharge PD DLL .................................................................................................19
8.3.2
Mode Register MR1 .........................................................................................................19
8.3.2.1
DLL Enable/Disable................................................................................................20
8.3.2.2
Output Driver Impedance Control ...........................................................................20
8.3.2.3
ODT RTT Values ....................................................................................................20
8.3.2.4
Additive Latency (AL) .............................................................................................20
8.3.2.5
Write leveling ..........................................................................................................20
8.3.2.6
Output Disable........................................................................................................21
8.3.2.7
TDQS, TDQS#........................................................................................................21
8.3.3
Mode Register MR2 .........................................................................................................22
8.3.3.1
Partial Array Self Refresh (PASR) ..........................................................................23
8.3.3.2
CAS Write Latency (CWL) ......................................................................................23
8.3.3.3
Auto Self Refresh (ASR) and Self Refresh Temperature (SRT) .............................23
8.3.3.4
Dynamic ODT (Rtt_WR) .........................................................................................23
8.3.4
Mode Register MR3 .........................................................................................................24
8.3.4.1
Multi Purpose Register (MPR) ................................................................................24
8.4 No OPeration (NOP) Command..........................................................................................................25
8.5 Deselect Command.............................................................................................................................25
8.6 DLL-off Mode ......................................................................................................................................25
8.7 DLL on/off switching procedure...........................................................................................................26
8.7.1
DLL “on” to DLL “off” Procedure ..........................................................................26
8.7.2
DLL “off” to DLL “on” Procedure ..........................................................................27
8.8 Input clock frequency change..............................................................................................................28
8.8.1
Frequency change during Self-Refresh............................................................................28
8.8.2
Frequency change during Precharge Power-down ..........................................................28
Publication Release Date: Jan. 20, 2015
Revision: A05
-1-