W632GU8KB Datasheet, PDF (10/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
B3, C7,C2, C8, E3,
E8, D2, E7
DQ0−DQ7
Input/Output Data Input/Output: Lower byte of Bi-directional data bus.
C3, D3
DQS, DQS#
Input/Output
Data Strobe: Output with read data, input with write data. Edge-
aligned with read data, centered in write data. DQS is paired with
DQS# to provide differential pair signaling to the system during read
and write data transfer. DDR3L SDRAM supports differential data
strobe only and does not support single-ended.
B7, A7
TDQS, TDQS#
Output
Termination Data Strobe: When TDQS enabled via Mode Register
A11 = 1 in MR1, the DRAM will enable the same termination
resistance function on TDQS/TDQS# that is applied to DQS/DQS#.
When TDQS disabled via mode register A11 = 0 in MR1, DM/TDQS
will provide the data mask function and TDQS# is not used.
A2, A9, D7, G2, G8,
K1, K9, M1, M9
VDD
Supply
Power Supply: 1.283V to 1.45V operational.
A1, A8, B1, D8, F2,
F8, J1, J9, L1, L9,
VSS
N1, N9
Supply
Ground.
B9, C1, E2, E9
VDDQ
Supply
DQ Power Supply: 1.283V to 1.45V operational.
B2, B8, C9, D1, D9
VSSQ
Supply
DQ Ground.
E1
VREFDQ
Supply
Reference voltage for DQ.
J8
VREFCA
Supply
Reference voltage for Control, Command and Address inputs.
External reference ball for output drive and On-Die Termination
H8
ZQ
Supply
Impedance calibration: This ball needs an external 240 Ω ± 1%
external resistor (RZQ), connected from this ball to ground to perform
ZQ calibration.
A3, F1, F9, H1, H9,
J7
NC
No Connect: No internal electrical connection is present.
Note:
Input only balls (BA0-BA2, A0-A14, RAS#, CAS#, WE#, CS#, CKE, ODT and RESET#) do not supply termination.
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Publication Release Date: Jan. 20, 2015
Revision: A05