W632GU8KB Datasheet, PDF (53/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
CK#
CK
Command^*3
Address^*4
DQS, DQS#
T0
T1
T3
T4
T5
T6
READ
Bank
Col n
NOP
NOP
NOP
READ
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
NOP
tRPRE
T7
WRITE
Bank
Col b
T8
NOP
T9
T10
NOP
NOP
tRPST
T11
T12
NOP
NOP
tWPRE
T13
T14
T15
NOP
NOP
4 clocks
NOP
tWPST
DQ^*2
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
WL = 5
Din
Din
Din
Din
b
b+1 b+2
b+7
NOTES: 1. RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, Din b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T7.
TIME BREAK
TRANSITIONING DATA
T16
NOP
tWR
tWTR
DON'T CARE
Figure 37 – READ (BL8) to WRITE (BC4) OTF
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Publication Release Date: Jan. 20, 2015
Revision: A05