W632GU8KB Datasheet, PDF (114/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.9.4 Design guide lines for RTTPU and RTTPD
Table 36 provides an overview of the ODT DC electrical pull-up and pull-down characteristics. The
values are not specification requirements, but can be used as design guide lines.
Table 36 – ODT DC Electrical Pull-Down and Pull-Up Characteristics, assuming RZQ = 240 Ω ± 1%
entire operating temperature range; after proper ZQ calibration
MR1 A9, A6, A2 RTT Resistor
Vout
Min. Nom. Max.
Unit
Notes
0, 1, 0
120 Ω, RTT120PD240, VOLDC = 0.2 × VDDQ 0.6 1.0 1.15 RZQ/TISFPUPD 1, 2, 3, 4, 5
0, 0, 1
60 Ω, RTT60PD120, VOMDC = 0.5 × VDDQ 0.9 1.0 1.15 RZQ/TISFPUPD 1, 2, 3, 4, 5
0, 1, 1
40 Ω, RTT40PD80,
VOHDC = 0.8 × VDDQ 0.9 1.0 1.45 RZQ/TISFPUPD 1, 2, 3, 4, 5
1, 0, 1
30 Ω, RTT30PD60,
1, 0, 0
20 Ω RTT20PD40
RTT120PU240, VOLDC = 0.2 × VDDQ 0.9 1.0 1.45 RZQ/TISFPUPD 1, 2, 3, 4, 5
RTT60PU120, VOMDC = 0.5 × VDDQ 0.9 1.0 1.15 RZQ/TISFPUPD 1, 2, 3, 4, 5
RTT40PU80,
VOHDC = 0.8 × VDDQ 0.6 1.0 1.15 RZQ/TISFPUPD 1, 2, 3, 4, 5
RTT30PU60,
RTT20PU40
Notes:
1. TISF_PUPD: Termination Impedance Scaling Factor for Pull-Up and Pull-Down path:
TISF_PUPD = 1 for RTT_120PU/PD240
TISF_PUPD = 2 for RTT_60PU/PD120
TISF_PUPD = 3 for RTT_40PU/PD80
TISF_PUPD = 4 for RTT_30PU/PD60
TISF_PUPD = 6 for RTT_20PU/PD40
2. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance
limits if temperature or voltage changes after calibration, see the above section ODT temperature and voltage sensitivity.
3. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS.
4. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5 × VDDQ. Other calibration schemes may be
used to achieve the linearity spec shown above, e.g. calibration at 0.2 × VDDQ and 0.8 × VDDQ.
5. Not a specification requirement, but a design guide line.
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Publication Release Date: Jan. 20, 2015
Revision: A05