W632GU8KB Datasheet, PDF (65/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
8.15 Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3L SDRAMs. This command
is non persistent, so it must be issued each time a refresh is required. The DDR3L SDRAM requires
Refresh cycles at an average periodic interval of tREFI. When CS#, RAS# and CAS# are held Low and
WE# High at the rising edge of the clock, the chip enters a Refresh cycle. All banks of the SDRAM
must be precharged and idle for a minimum of the precharge time tRP(min) before the Refresh
Command can be applied. The refresh addressing is generated by the internal refresh controller. This
makes the address bits “Don't Care” during a Refresh command. An internal address counter supplies
the addresses during the refresh cycle. No control of the external address bus is required once this
cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the
precharged (idle) state. A delay between the Refresh Command and the next valid command, except
NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as shown in
Figure 55. Note that the tRFC timing parameter depends on memory density.
In general, a Refresh command needs to be issued to the DDR3L SDRAM regularly every tREFI
interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in
the absolute refresh interval is provided. A maximum of 8 Refresh commands can be postponed
during operation of the DDR3L SDRAM, meaning that at no point in time more than a total of 8
Refresh commands are allowed to be postponed. In case that 8 Refresh commands are postponed in
a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 ×
tREFI (see Figure 56). A maximum of 8 additional Refresh commands can be issued in advance
(“pulled in”), with each one reducing the number of regular Refresh commands required later by one.
Note that pulling in more than 8 Refresh commands in advance does not further reduce the number of
regular Refresh commands required later, so that the resulting maximum interval between two
surrounding Refresh commands is limited to 9 × tREFI (see Figure 57). At any given time, a maximum
of 16 REF commands can be issued within 2 x tREFI. Self-Refresh Mode may be entered with a
maximum of eight Refresh commands being postponed. After exiting Self-Refresh Mode with one or
more Refresh commands postponed, additional Refresh commands may be postponed to the extent
that the total number of postponed Refresh commands (before and after the Self-Refresh) will never
exceed eight. During Self-Refresh Mode, the number of postponed or pulled-in REF commands does
not change.
T0
T1
CK#
CK
Ta0
Ta1
Tb0
Tb1
Tb2
Tb3
Tc0
Tc1
Tc2
Tc3
Command
REF
NOP
NOP
REF
NOP
NOP
VALID
VNAOLPID
VALID
VALID
VALID
REF
VALID
VALID
VALID
tRFC
tRFC(min)
DRAM must be idle
tREFI (max. 9 x tREFI)
DRAM must be idle
NOTES: 1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
Figure 55 – Refresh Command Timing
TIME BREAK
DON'T CARE
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Publication Release Date: Jan. 20, 2015
Revision: A05