W632GU8KB Datasheet, PDF (18/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
Table 1 – Burst Type and Burst Order
Burst
Length
4
Chop
8
READ/
WRITE
READ
WRITE
READ
WRITE
Starting Column Address
(A2, A1, A0)
000
001
010
011
100
101
110
111
0,V,V
1,V,V
000
001
010
011
100
101
110
111
V,V,V
Burst type = Sequential
(decimal)
A3 = 0
0,1,2,3,T,T,T,T
1,2,3,0,T,T,T,T
2,3,0,1,T,T,T,T
3,0,1,2,T,T,T,T
4,5,6,7,T,T,T,T
5,6,7,4,T,T,T,T
6,7,4,5,T,T,T,T
7,4,5,6,T,T,T,T
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
0,1,2,3,4,5,6,7
1,2,3,0,5,6,7,4
2,3,0,1,6,7,4,5
3,0,1,2,7,4,5,6
4,5,6,7,0,1,2,3
5,6,7,4,1,2,3,0
6,7,4,5,2,3,0,1
7,4,5,6,3,0,1,2
0,1,2,3,4,5,6,7
Burst type = Interleaved
(decimal)
A3 = 1
0,1,2,3,T,T,T,T
1,0,3,2,T,T,T,T
2,3,0,1,T,T,T,T
3,2,1,0,T,T,T,T
4,5,6,7,T,T,T,T
5,4,7,6,T,T,T,T
6,7,4,5,T,T,T,T
7,6,5,4,T,T,T,T
0,1,2,3,X,X,X,X
4,5,6,7,X,X,X,X
0,1,2,3,4,5,6,7
1,0,3,2,5,4,7,6
2,3,0,1,6,7,4,5
3,2,1,0,7,6,5,4
4,5,6,7,0,1,2,3
5,4,7,6,1,0,3,2
6,7,4,5,2,3,0,1
7,6,5,4,3,2,1,0
0,1,2,3,4,5,6,7
NOTES
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 4, 5
1, 2, 4, 5
2
2
2
2
2
2
2
2
2, 4
Notes:
1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being
selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation.
This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
2. 0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
3. T: Output driver for data and strobes are in high impedance.
4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
5. X: Don't Care.
8.3.1.2 CAS Latency
The CAS Latency is defined by MR0 (bits A2, A4, A5 and A6) as shown in Figure 5. CAS Latency is
the delay, in clock cycles, between the internal Read command and the availability of the first bit of
output data. DDR3L SDRAM does not support any half-clock latencies. The overall Read Latency (RL)
is defined as Additive Latency (AL) + CAS Latency (CL); RL = AL + CL. For more information on the
supported CL and AL settings based on the operating clock frequency, refer to section 10.15 “Speed
Bins” on page 133. For detailed Read operation refer to section 8.13 “READ Operation” on page 43.
8.3.1.3 Test Mode
The normal operating mode is selected by MR0 (bit A7 = 0) and all other bits set to the desired values
shown in Figure 5. Programming bit A7 to a ‘1’ places the DDR3L SDRAM into a test mode that is only
used by the DRAM Manufacturer and should NOT be used. No operations or functionality is specified
if A7 = 1.
8.3.1.4 DLL Reset
The DLL Reset bit is self-clearing, meaning that it returns back to the value of ‘0’ after the DLL reset
function has been issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Any
time that the DLL reset function is used, tDLLK must be met before any functions that require the DLL
can be used (i.e., Read commands or ODT synchronous operations).
- 18 -
Publication Release Date: Jan. 20, 2015
Revision: A05