W632GU8KB Datasheet, PDF (144/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
AC Timing and Operating Condition for -12/12I/-15/15I speed grades, continued
SYMBOL
SPEED GRADE
PARAMETER
DDR3L-1600
(-12/12I)
MIN.
MAX.
DDR3L-1333
(-15/15I)
MIN.
MAX.
UNITS NOTES
Power Down Timing
tXP
Exit Power Down with DLL on to any valid
command; Exit Precharge Power Down with DLL
frozen to commands not requiring a locked DLL
max(3nCK,
6nS)

max(3nCK,
6nS)

34
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK,
24nS)

max(10nCK,
24nS)

35
tCKE CKE minimum pulse width
max(3nCK,
5nS)

max(3nCK,
5.625nS)

tCPDED Command pass disable delay
1

1

nCK
tPD Power Down Entry to Exit Timing
tCKE(min) 9 * tREFI tCKE(min) 9 * tREFI
25
tACTPDEN Timing of ACT command to Power Down entry
1

1

nCK
27
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
1

1

nCK
27
tRDPDEN Timing of RD/RDA command to Power Down entry RL + 4 + 1

RL + 4 + 1

nCK
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.: 
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + WR + 1
Max.: 
nCK
19
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.: 
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 + WR + 1
Max.: 
nCK
19
tREFPDEN Timing of REF command to Power Down entry
1

1

nCK 27, 28
tMRSPDEN Timing of MRS command to Power Down entry
tMOD(min)

tMOD(min)

ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4

4

nCK
30
ODTH8
tAONPD
ODT high time with Write command and burst
length 8
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
6

6

nCK
31
2
8.5
2
8.5
nS
32
tAOFPD
tAON
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
RTT turn-on
2
8.5
2
8.5
nS
32
-225
225
-250
250
pS 17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
0.3
0.7 tCK(avg) 17, 44
tADC RTT dynamic change skew
0.3
0.7
0.3
0.7 tCK(avg) 17
Write Leveling Timing
tWLMRD
First DQS/DQS# rising edge after write leveling
mode is programmed
40

40

nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
25

25

nCK
5
165

195

pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
165

195
tWLO Write leveling output delay
0
7.5
0

pS
9
nS
tWLOE Write leveling output error
0
2
0
2
nS
- 144 -
Publication Release Date: Jan. 20, 2015
Revision: A05