W632GU8KB Datasheet, PDF (60/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
T0
T1
CK#
CK
Command^*3
WRITE
NOP
Address^*4
Bank
Col a
DQS, DQS#
DQ^*2
T2
T3
NOP
NOP
WL = 5
T4
T5
T6
T7
NOP
NOP
NOP
NOP
tWPRE
tWPST
Din
Din
Din
Din
n
n+1
n+2
n+3
T8
T9
Tn
NOP
tWTR^*5
NOP
READ
Bank
Col b
RL = 6
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data
shown at T7.
Figure 45 – WRITE (BC4) to READ (BC4) Operation
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Tn
CK#
CK
Command^*3
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
PRE
tWR^*5
Address^*4
Bank
Col n
tWPRE
tWPST
DQS, DQS#
DQ^*2
WL = 5
Din
Din
Din
Din
n
n+1
n+2
n+3
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Notes:
1. BC4, WL = 5, RL = 6.
2. Din n = data-in from column n; Dout b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 10 during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies
the last burst write cycle until the precharge command can be issued to the same bank.
Figure 46 – WRITE (BC4) to PRECHARGE Operation
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Publication Release Date: Jan. 20, 2015
Revision: A05