W632GU8KB Datasheet, PDF (140/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
AC Timing and Operating Condition for -11 speed grade, continued
SYMBOL
SPEED GRADE
PARAMETER
DDR3L-1866 (-11)
MIN.
MAX.
UNITS NOTES
Power Down Timing
Exit Power Down with DLL on to any valid
tXP command; Exit Precharge Power Down with DLL max(3nCK, 6nS)

34
frozen to commands not requiring a locked DLL
tXPDLL
Exit Precharge Power Down with DLL frozen to
commands requiring a locked DLL
max(10nCK, 24nS)

35
tCKE CKE minimum pulse width
max(3nCK, 5nS)

tCPDED Command pass disable delay
2

nCK
tPD Power Down Entry to Exit Timing
tCKE(min)
9 * tREFI
25
tACTPDEN Timing of ACT command to Power Down entry
1

nCK
27
tPRPDEN
Timing of PRE or PREA command to Power Down
entry
1

nCK
27
tRDPDEN Timing of RD/RDA command to Power Down entry
RL + 4 + 1

nCK
tWRPDEN
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + roundup (tWR(min)/ tCK(avg))
Max.: 
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Min.: WL + 4 + WR + 1
Max.: 
nCK
19
tWRPDEN
Timing of WR command to Power Down entry
(BC4MRS)
Min.: WL + 2 + roundup (tWR(min)/ tCK(avg))
Max.: 
nCK
20
tWRAPDEN
Timing of WRA command to Power Down entry
(BC4MRS)
Min.: WL + 2 + WR + 1
Max.: 
nCK
19
tREFPDEN Timing of REF command to Power Down entry
1

nCK 27, 28
tMRSPDEN Timing of MRS command to Power Down entry
tMOD(min)

ODT Timing
ODTH4
ODT high time without write command or with write
command and burst chop 4
4

nCK
30
ODTH8
ODT high time with Write command and burst
length 8
6

nCK
31
tAONPD
Asynchronous RTT turn-on delay (Power Down
with DLL frozen)
2
8.5
nS
32
tAOFPD
Asynchronous RTT turn-off delay (Power Down
with DLL frozen)
2
8.5
nS
32
tAON RTT turn-on
-195
195
pS 17, 43
tAOF
Rtt_Nom and Rtt_WR turn-off time from ODTLoff
reference
0.3
0.7
tCK(avg) 17, 44
tADC RTT dynamic change skew
0.3
0.7
tCK(avg) 17
Write Leveling Timing
tWLMRD
First DQS/DQS# rising edge after write leveling
mode is programmed
40

nCK
5
tWLDQSEN
DQS/DQS# delay after write leveling mode is
programmed
25

nCK
5
tWLS
Write leveling setup time from (CK, CK#) zero
crossing to rising (DQS, DQS#) zero crossing
140

pS
tWLH
Write leveling hold time from rising (DQS, DQS#)
zero crossing to (CK, CK#) zero crossing
140

pS
tWLO Write leveling output delay
0
7.5
nS
tWLOE Write leveling output error
0
2
nS
- 140 -
Publication Release Date: Jan. 20, 2015
Revision: A05