W632GU8KB Datasheet, PDF (86/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
CK#
CK
Command
Address
ODT
RTT
DQS, DQS#
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ODTH4
ODTLon
ODTLoff
tAONmin
tAONmax
Rtt_Nom
tAOFmin
tAOFmax
TRANSITIONING
DON'T CARE
Notes:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
Figure 78 – Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
CK#
CK
Command
Address
ODT
RTT
DQS, DQS#
DQ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
NOP
WRS8
VALID
ODTLcnw
NOP
NOP
ODTLon
NOP
NOP
NOP
ODTH8
NOP
NOP
NOP
ODTLoff
tAONmin
ODTLcwn8
tADCmax
Rtt_WR
T10
T11
NOP
NOP
tAOFmin
tAOFmax
WL
Din Din
Din
Din Din
Din Din
Din
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
TRANSITIONING
DON'T CARE
Note:
1. Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
Figure 79 – Dynamic ODT: Behavior with ODT pin being asserted together with write command
for a duration of 6 clock cycles
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Publication Release Date: Jan. 20, 2015
Revision: A05