W632GU8KB Datasheet, PDF (124/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
Basic IDD and IDDQ Measurement Conditions, continued
SYM. DESCRIPTION
IDD4R
IDDQ4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
IDD8
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8^(1,6); AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 45; Data IO:
seamless read data burst with different data between one burst and the next one according to Table
45; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,... (see Table 44); Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT Signal:
stable at 0; Pattern Details: see Table 45
Operating Burst Read IDDQ Current
Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 39; BL: 8⁽¹⁾; AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 46; Data IO:
seamless write data burst with different data between one burst and the next one according to
Table 46; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,... (see Table 46); Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT Signal:
stable at HIGH; Pattern Details: see Table 46
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 39; BL: 8⁽¹⁾; AL: 0; CS#: High between
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 47; Data
IO: MID-LEVEL; DM: stable at 0; Bank Activity: REF command every nRFC (see Table 47);
Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT Signal: stable at 0; Pattern Details:
see Table 47
Self Refresh Current: Normal Temperature Range
TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabled⁽⁴⁾; Self-Refresh Temperature Range (SRT):
Normal⁽⁵⁾; CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 39; BL: 8⁽¹⁾; AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers⁽²⁾; ODT Signal: MID-
LEVEL
Self-Refresh Current: Extended Temperature Range
TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabled⁽⁴⁾; Self-Refresh Temperature Range (SRT):
Extended⁽⁵⁾; CKE: Low; External clock: Off; CK and CK#: LOW; CL: see Table 39; BL: 8⁽¹⁾; AL: 0;
CS#, Command, Address, Bank Address, Data IO: MID-LEVEL; DM: stable at 0; Bank Activity:
Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode
Registers⁽²⁾; ODT Signal: MID-LEVEL
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 39; BL:
8^(1,6); AL: CL-1; CS#: High between ACT and RDA; Command, Address, Bank Address Inputs:
partially toggling according to Table 48; Data IO: read data bursts with different data between one
burst and the next one according to Table 48; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1, ...7) with different addressing, see Table 48; Output Buffer and RTT:
Enabled in Mode Registers⁽²⁾; ODT Signal: stable at 0; Pattern Details: see Table 48
RESET# Low Current
RESET#: Low; External clock: Off; CK and CK#: Low; CKE: FLOATING; CS#, Command,
Address, Bank Address, Data IO: FLOATING; ODT Signal: FLOATING
RESET# Low current reading is valid once power is stable and RESET has been Low for at least
1mS
Notes:
1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00b.
2. Output Buffer Enable: set MR1 A[12] = 0b; set MR1 A[5,1] = 01b; Rtt_Nom enable: set MR1 A[9,6,2] = 011b; Rtt_WR
enable: set MR2 A[10,9] = 10b.
3. Pecharge Power Down Mode: set MR0 A12=0b for Slow Exit or MR0 A12=1b for Fast Exit.
4. Auto Self-Refresh (ASR): set MR2 A6 = 0b to disable or 1b to enable feature.
5. Self-Refresh Temperature Range (SRT): set MR2 A7=0b for normal or 1b for extended temperature range.
6. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0b.
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Publication Release Date: Jan. 20, 2015
Revision: A05