W632GU8KB Datasheet, PDF (51/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
CK#
CK
Command^*3
Address^*4
DQS, DQS#
DQ^*2
T0
T1
T3
T4
T5
T6
T7
T8
READ
NOP
NOP
NOP
WRITE
READ to WRITE Command Delay = RL + tCCD / 2 + 2tCK - WL
NOP
Bank
Col n
Bank
Col b
tRPRE
NOP
NOP
tRPST
RL = 6
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
WL = 5
T9
T10
T11
T12
T13
NOP
NOP
tWPRE
NOP
NOP
4 clocks
NOP
tWPST
Din
Din
Din
Din
b
b+1
b+2
b+3
T14
NOP
T15
T16
NOP
tWR
tWTR
NOP
NOTES: 1. BC4, RL = 6 (CL = 6, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. Dout n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T0 and WRITE command at T5.
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 33 – READ (BC4) to WRITE (BC4) OTF
CK#
CK
Command^*3
Address^*4
DQS, DQS#
DQ^*2
T0
READ
Bank
Col n
T1
NOP
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
NOP
tCCD
NOP
READ
Bank
Col b
NOP
NOP
tRPRE
NOP
NOP
NOP
NOP
NOP
NOP
tRPST
RL = 6
Dout
n
Dout
n+1
Dout
n+2
RL = 6
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
T13
NOP
NOTES: 1. RL = 6 (CL = 6, AL = 0).
2. Dout n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0 A[1:0] = 01 and A12 = 1 during READ command at T0.
BC4 setting activated by MR0 A[1:0] = 01 and A12 = 0 during READ command at T4.
TRANSITIONING DATA
Figure 34 – READ (BL8) to READ (BC4) OTF
T14
NOP
DON'T CARE
- 51 -
Publication Release Date: Jan. 20, 2015
Revision: A05