W632GU8KB Datasheet, PDF (105/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
Table 23 – Cross point voltage for differential input signals (CK, DQS)
PARAMETER
SYMBOL
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK#
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS#
VIX(CK)
VIX(DQS)
DDR3L-1333/1600/1866
MIN.
MAX.
-150
150
-150
150
UNIT NOTES
mV
1
mV
Note:
1. The relation between VIX Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + VIX (Min) - VSEL ≥ 25mV
VSEH - ((VDD/2) + VIX (Max)) ≥ 25mV
10.6.6 Slew Rate Definitions for Single-Ended Input Signals
See section 10.16.4 “Address / Command Setup, Hold and Derating” on page 148 for single-
ended slew rate definitions for address and command signals.
See section 10.16.5 “Data Setup, Hold and Slew Rate Derating” on page 155 for single-ended slew
rate definitions for data signals.
10.6.7 Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown
in Table 24 and Figure 93.
Table 24 – Differential Input Slew Rate Definition
Description
Measured
from
to
Defined by
Differential input slew rate for rising edge
(CK - CK# and DQS - DQS#)
VIL.DIFFmax VIH.DIFFmin [VIH.DIFFmin - VIL.DIFFmax] / ΔTR.DIFF
Differential input slew rate for falling edge
(CK - CK# and DQS - DQS#)
VIH.DIFFmin VIL.DIFFmax
[VIH.DIFFmin - VIL.DIFFmax] / ΔTF.DIFF
Note: The differential signal (i.e., CK - CK# and DQS - DQS#) must be linear between these thresholds
ΔTR.DIFF
VIH.DIFFmin
0
VIL.DIFFmax
ΔTF.DIFF
Figure 93 – Differential Input Slew Rate Definition for DQS, DQS# and CK, CK#
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Publication Release Date: Jan. 20, 2015
Revision: A05