W632GU8KB Datasheet, PDF (56/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
8.14 WRITE Operation
8.14.1 DDR3L Burst Operation
During a READ or WRITE command, DDR3L will support BC4 and BL8 on the fly using address A12
during the READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12 = 0, BC4 (BC4 = burst chop, tCCD = 4)
A12 = 1, BL8
A12 is used only for burst length control, not as a column address.
8.14.2 WRITE Timing Violations
8.14.2.1 Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be
initiated to make sure that the DRAM works properly. However, it is desirable; for certain minor
violations, that the DRAM is guaranteed not to “hang up”, and that errors are limited to that particular
operation.
For the following, it will be assumed that there are no timing violations with regards to the Write
command itself (including ODT, etc.) and that it does satisfy all timing requirements not mentioned
below.
8.14.2.2 Data Setup and Hold Violations
Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges
associated with a write burst, and then wrong data might be written to the memory location addressed
with this WRITE command.
In the example (Figure 40 on page 57), the relevant strobe edges for write burst A are associated with
the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5.
Subsequent reads from that location might result in unpredictable read data, however the DRAM will
work properly otherwise.
8.14.2.3 Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing
requirements (tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst,
then wrong data might be written to the memory location addressed with the offending WRITE
command. Subsequent reads from that location might result in unpredictable read data, however the
DRAM will work properly otherwise.
In the example (Figure 48 on page 61) the relevant strobe edges for Write burst n are associated with
the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements
starting or ending on one of these strobe edges need to be fulfilled for a valid burst. For Write burst b
the relevant edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges
are associated withboth bursts.
8.14.2.4 Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a Write burst. No
actual timing violations are shown here. For a valid burst all timing parameters for each edge of a
burst need to be satisfied (not only for one edge - as shown).
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Publication Release Date: Jan. 20, 2015
Revision: A05