W632GU8KB Datasheet, PDF (136/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.15.4 Speed Bin General Notes
The absolute specification for all speed bins is TOPER and VDD = VDDQ = 1.283V to 1.45V. In addition
the following general notes apply.
1. Max. limits are exclusive. E.g. if tCK(AVG).MAX value is 2.5 nS, tCK(AVG) needs to be < 2.5 nS.
2. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making
a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as
requirements from CWL setting.
3. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are
synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An
application should use the next smaller standard tCK(AVG) value (2.5, 1.875, 1.5, 1.25 or 1.07 nS)
when calculating CL [nCK] = tAA [nS] / tCK(AVG) [nS], rounding up to the next ‘Supported CL’.
4. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG)
down to the next valid speed bin (i.e. 3.3nS or 2.5nS or 1.875 nS, 1.5 nS or 1.25 nS). This result is
tCK(AVG).MAX corresponding to CL SELECTED.
5. ‘Reserved’ settings are not allowed. User must program a different value.
6. Any DDR3L-1333 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3L-1600 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3L-1866 speed bin also supports functional operation at lower frequencies as shown in the
table which are not subject to Production Tests but verified by Design/Characterization.
9. For devices supporting optional down binning to CL=7 and CL=9, tAA/tRCD/tRP min must be 13.125
nS or lower. SPD settings must be programmed to match. For example, DDR3L-1333 (9-9-9)
devices supporting down binning to DDR3L-1066 (7-7-7) should program 13.125 nS in SPD bytes
for tAAmin (Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3L-1600 (11-11-11) devices
supporting down binning to DDR3L-1333 (9-9-9) or DDR3L-1066 (7-7-7) should program 13.125 nS
in SPD bytes for tAAmin (Byte16), tRCDmin (Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is
programmed to 13.125 nS, tRCmin (Byte 21, 23) also should be programmed accodingly. For
example, 49.125nS (tRASmin + tRPmin = 36 nS + 13.125 nS) for DDR3L-1333 (9-9-9) and 48.125
nS (tRASmin + tRPmin = 35 nS + 13.125 nS) for DDR3L-1600 (11-11-11).
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Publication Release Date: Jan. 20, 2015
Revision: A05