W632GU8KB Datasheet, PDF (106/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.7 DC and AC Output Measurement Levels
Table 25 – Single-ended DC and AC Output Levels
PARAMETER
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output slew rate)
AC output low measurement level (for output slew rate)
SYMBOL
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
VALUE
0.8 x VDDQ
0.5 x VDDQ
0.2 x VDDQ
VTT + 0.1 x VDDQ
VTT - 0.1 x VDDQ
UNIT NOTES
V
V
V
V
1
V
1
Note:
1. The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 26 – Differential DC and AC Output Levels
PARAMETER
AC differential output high measurement level (for output
slew rate)
AC differential output low measurement level (for output
slew rate)
SYMBOL
VOH.DIFF(AC)
VOL.DIFF(AC)
VALUE
MIN. MAX.
UNIT NOTES
+0.2 x VDDQ
V
1
-0.2 x VDDQ
V
1
Note:
1. The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 34 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
10.7.1 Output Slew Rate Definition and Requirements
The slew rate definition depends if the signal is single-ended or differential. For the relevant AC output
reference levels see above Table 25 and Table 26.
Table 27 – Output Slew Rate
PARAMETER
SYMBOL
Single-ended Output Slew Rate SRQse
DDR3L-1333/1600/1866
MIN.
MAX.
1.75
5¹⁾
UNIT
V/nS
NOTES
1, 2, 3
Differential Output Slew Rate SRQdiff
3.5
12
V/nS
1, 2, 3
Notes:
1. In two cases, a maximum slew rate of 6 V/nS applies for a single DQ signal within a byte lane.
- Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e they stay at either high or low).
- Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high
to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 5 V/nS applies.
2. Background for Symbol Nomenclature: SR: Slew Rate; Q: Query Output (like in DQ, which stands for Data-in, Query-
Output); se: Single-ended Signals; diff: Differential Signals.
3. For RON = RZQ/7 settings only.
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Publication Release Date: Jan. 20, 2015
Revision: A05