W632GU8KB Datasheet, PDF (19/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
8.3.1.5 Write Recovery
The programmed WR value MR0 (bits A9, A10 and A11) is used for the auto precharge feature along
with tRP to determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by
dividing tWR (in nS) by tCK(avg) (in nS) and rounding up to the next integer: WRmin[cycles] =
Roundup(tWR[nS]/tCK(avg)[nS]). The WR must be programmed to be equal to or larger than tWR(min).
8.3.1.6 Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power down mode. When MR0 (A12
= 0), or ‘slow-exit’, the DLL is frozen after entering precharge power down (for potential power savings)
and upon exit requires tXPDLL to be met prior to the next valid command. When MR0 (A12 = 1), or
‘fast-exit’, the DLL is maintained after entering precharge power down and upon exiting power down
requires tXP to be met prior to the next valid command.
8.3.2 Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength,
Rtt_Nom impedance, additive latency, Write leveling enable, TDQS enable and Qoff. The Mode
Register 1 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA0 and low on BA1 and
BA2, while controlling the states of address pins according to the Figure 6 below.
BA2 BA1 BA0 A14 A13 A12 A11 A10
A9 A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*¹
0
1
0*¹
Qoff TDQS 0*¹ Rtt_Nom 0*¹ Level Rtt_Nom D.I.C
AL
Rtt_Nom D.I.C DLL
Mode Register 1
BA1 BA0
0
0
0
1
1
0
1
1
MR Select
MR0
MR1
MR2
MR3
A7 Write leveling enable
0
Disabled
1
Enabled
A11 TDQS enable
0
Disable
1
Enable
A12
Qoff^*2
0
Output buffer enabled
1 Output buffer disabled^*2
A9 A6 A2
Rtt_Nom^*3
0
0
0 Rtt_Nom disabled
0
0
1
RZQ/4
0
1
0
RZQ/2
0
1
1
RZQ/6
1
0
0
RZQ/12*⁴
1
0
1
RZQ/8*⁴
1
1
0
Reserved
1
1
1
Reserved
Note: RZQ = 240 ohms
A0 DLL Enable
0
Enable
1
Disable
Output Driver
A5 A1 _{Impedance Control}
00
RZQ/6
01
RZQ/7
10
Reserved
11
Reserved
Note: RZQ = 240 ohms
A4 A3 Additive Latency
0
0
0 (AL disabled)
01
CL-1
10
CL-2
11
Reserved
Notes:
1. BA2, A8, A10, A13 and A14 are reserved for future use and must be programmed to “0” during MRS.
2. Outputs disabled - DQs, DQSs, DQS#s.
3. In Write leveling Mode (MR1 A[7] = 1) with MR1 A[12]=1, all Rtt_Nom settings are allowed; in Write Leveling Mode (MR1 A[7]
= 1) with MR1 A[12]=0, only Rtt_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
4. If Rtt_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
Figure 6 – MR1 Definition
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Publication Release Date: Jan. 20, 2015
Revision: A05