W632GU8KB Datasheet, PDF (145/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.16.3 Timing Parameter Notes
1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents
one clock cycle of the input clock, counting the actual clock edges.
For example, tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another
Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) +
tERR(4per),min (which is smaller than 4 x tCK(avg)).
2. Timing that is not specified is illegal and after such an event, in order to provide proper operation, the
DRAM must be resetted or powered down and then restarted through the specified initialization
sequence before normal operation can continue.
3. The CK/CK# input reference level (for timing reference to CK / CK#) is the point at which CK and CK#
cross.
The DQS/DQS# input reference level is the point at which DQS and DQS# cross;
The input reference level for signals other than CK/CK#, DQS/DQS# and RESET# is VREFCA and
VREFDQ respectively.
4. Inputs are not recognized as valid until VREFCA stabilizes within specified limits.
5. The max values are system dependent.
6. tCK(avg) refers to the actual application clock period. WR refers to the WR parameter stored in mode
register MR0.
7. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
8. For these parameters, the DDR3L SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [nS] / tCK(avg)
[nS] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock
jitter specifications are met. This means: For DDR3L-1333 (9-9-9), of which tRP = 13.5nS, the device will
support tnRP = RU{tRP / tCK(avg)} = 9, as long as the input clock jitter specifications are met, i.e.
Precharge command at Tm and Active command at Tm+9 is valid even if (Tm+9 - Tm) is less than
13.5nS due to input clock jitter.
9. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are
not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are
relative to the clock signal crossing that latches the command/address. That is, these parameters
should be met whether clock jitter is present or not.
10.Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the
consecutive crossing of VREF(DC).
11.These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its
respective data strobe signal (DQS, DQS#) crossing.
12.tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from
one falling edge to the next consecutive rising edge.
13.tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured
from one rising edge to the next consecutive falling edge.
14.tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
15.tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing
parameter in the application.
16.These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its respective clock
signal (CK, CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters
should be met whether clock jitter is present or not.
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Publication Release Date: Jan. 20, 2015
Revision: A05