W632GU8KB Datasheet, PDF (84/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
Table 11 – Latencies and timing parameters relevant for Dynamic ODT
Name and Description
ODT turn-on Latency
ODT turn-off Latency
ODT Latency for changing
from Rtt_Nom to Rtt_WR
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 4)
ODT Latency for change from
Rtt_WR to Rtt_Nom (BL = 8)
Minimum ODT high time after
ODT assertion
Minimum ODT high time after
Write (BL = 4)
Minimum ODT high time after
Write (BL =8)
RTT change skew
Abbr.
ODTLon
ODTLoff
ODTLcnw
ODTLcwn4
ODTLcwn8
ODTH4
ODTH4
ODTH8
tADC
Defined from
Registering external
ODT signal high
Registering external
ODT signal low
Registering external
write command
Registering external
write command
Registering external
write command
Registering ODT
high
Registering Write
with ODT high
Registering Write
with ODT high
ODTLcnw
ODTLcwn
Defined to
Turning termination on
Definition for all DDR3L
speed bins
ODTLon = WL - 2
Turning termination off
ODTLoff = WL - 2
Change RTT strength from
Rtt_Nom to Rtt_WR
Change RTT strength from
Rtt_WR to Rtt_Nom
Change RTT strength from
Rtt_WR to Rtt_Nom
ODTLcnw = WL - 2
ODTLcwn4 = 4 + ODTLoff
ODTLcwn8 = 6 + ODTLoff
ODT registered low
ODTH4 = 4
ODT registered low
ODTH4 = 4
ODT registered low
RTT valid
ODTH4 = 6
tADC(min) = 0.3 * tCK(avg)
tADC(max) = 0.7 * tCK(avg)
Unit
tCK
tCK
tCK
tCK
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
tCK(avg)
Note: tAOFnom and tADCnom are 0.5 tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw and ODTLcwn)
8.19.3.2 ODT Timing Diagrams
The following pages provide exemplary timing diagrams as described in Table 12:
Table 12 – Timing Diagrams for “Dynamic ODT”
Figure and Page
Figure 77 on page 85
Figure 78 on page 86
Figure 79 on page 86
Figure 80 on page 87
Figure 81 on page 87
Description
Figure 77, Dynamic ODT: Behavior with ODT being asserted before and after the write
Figure 78, Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
Figure 79, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles
Figure 80, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 6 clock cycles, example for BC4 (via MRS or OTF), AL = 0, CWL = 5
Figure 81, Dynamic ODT: Behavior with ODT pin being asserted together with write command for a duration
of 4 clock cycles
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Publication Release Date: Jan. 20, 2015
Revision: A05