W632GU8KB Datasheet, PDF (121/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.13 IDD and IDDQ Specification Parameters and Test Conditions
10.13.1 IDD and IDDQ Measurement Conditions
In this section, IDD and IDDQ measurement conditions such as test load and patterns are defined.
Figure 105 shows the setup and test load for IDD and IDDQ measurements.
 IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the
DDR3L SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
 IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3L SDRAM under test tied together. Any IDD current is not included in IDDQ
currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3L SDRAM.
They can be used to support correlation of simulated IO power to actual IO power as
outlined in Figure 106. In DRAM module application, IDDQ cannot be measured separately
since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
 “0” and “LOW” is defined as VIN ≤ VILAC(max).
 “1” and “HIGH” is defined as VIN ≥ VIHAC(min).
 “MID-LEVEL” is defined as inputs are VREF = VDD / 2.
 Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 39.
 Basic IDD and IDDQ Measurement Conditions are described in Table 40.
 Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 41 through Table 48.
 IDD Measurements are done after properly initializing the DDR3L SDRAM. This includes but is not
limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0b (Output Buffer enabled in MR1);
Rtt_Nom = RZQ/6 (40 Ohm in MR1);
Rtt_WR = RZQ/2 (120 Ohm in MR2);
 Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time
before actual IDD or IDDQ measurement is started.
 Define D = {CS#, RAS#, CAS#, WE# } := {HIGH, LOW, LOW, LOW}
 Define D# = {CS#, RAS#, CAS#, WE# } := {HIGH, HIGH, HIGH, HIGH}
Table 39 – Timings used for IDD and IDDQ Measurement-Loop Patterns
Speed Bin
DDR3L-1333
DDR3L-1600
DDR3L-1866
CL-nRCD-nRP
9-9-9
11-11-11
13-13-13
Unit
Part Number Extension
-15/15I
-12/12I
-11
tCK
1.5
1.25
1.07
nS
CL
9
11
13
nCK
nRCD
9
11
13
nCK
nRC
33
39
45
nCK
nRAS
24
28
32
nCK
nRP
9
11
13
nCK
nFAW
20
24
26
nCK
nRRD
4
5
5
nCK
nRFC 2 Gb
107
128
150
nCK
- 121 -
Publication Release Date: Jan. 20, 2015
Revision: A05