W632GU8KB Datasheet, PDF (102/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

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10.6.3 Differential swing requirements for clock (CK - CK#) and strobe (DQS - DQS#)
Table 20 – Differential DC and AC Input Level
PARAMETER
SYM.
Differential input high
Differential input low
Differential input high AC
Differential input low AC
VIH.DIFF
VIL.DIFF
VIH.DIFF(AC)
VIL.DIFF(AC)
DDR3L-1333/1600/1866
MIN.
MAX.
+0.180
Note 3
Note 3
-0.180
2 x (VIH(AC) - VREF)
Note 3
Note 3
2 x (VIL(AC) - VREF)
UNIT NOTES
V
1
V
1
V
2
V
2
Notes:
1. Used to define a differential signal slew-rate.
2. For CK - CK# use VIH.CA(AC)/VIL.CA(AC) of ADD/CMD and VREFCA; for DQS, DQS# use VIH.DQ(AC)/VIL.DQ(AC) of DQs and
VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals CK, CK#, DQS, DQS# need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to
section 10.12 “Overshoot and Undershoot Specifications” on page 120.
VIHDIFF(AC)min
tDVAC
VIHDIFFmin
0
VILDIFFmax
Half cycle
VILDIFF(AC)max
tDVAC
time
Figure 90 – Definition of differential ac-swing and “time above AC-level” tDVAC
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Publication Release Date: Jan. 20, 2015
Revision: A05