W632GU8KB Datasheet, PDF (127/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
Table 43 – IDD2N and IDD3N Measurement-Loop Pattern¹
Data²
0
D
10000000000
-
1
0
2
D
10000000000
-
D#
111100000F0
-
3
D#
111100000F0
-
1
4-7
Repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
Repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
Repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
Repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
Repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-27
Repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
Repeat Sub-Loop 0, use BA[2:0] = 7 instead
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Table 44 – IDD2NT and IDDQ2NT Measurement-Loop Pattern¹
Data²
0
D
10000000000
-
1
0
2
D
10000000000
-
D#
111100000F0
-
3
D#
111100000F0
-
1
4-7
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
Repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-27
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
Repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
Notes:
1. DM must be driven LOW all the time. DQS, DQS# are MID-LEVEL.
2. DQ signals are MID-LEVEL.
- 127 -
Publication Release Date: Jan. 20, 2015
Revision: A05