W632GU8KB Datasheet, PDF (61/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
CK#
CK
Command^*3
Address^*4
DQS, DQS#
DQ^*2
T0
T1
WRITE
Bank
Col a
NOP
T2
T3
NOP
NOP
WL = 5
T4
T5
T6
T7
NOP
NOP
tWPRE
NOP
NOP
4 clocks
tWPST
Din Din Din Din
n n+1 n+2 n+3
NOTES:
1. BC4 on the fly, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 on the fly setting activated by MR0 A[1:0] = 01 and A12 = 0 during WRITE command at T0.
5. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).
T8
NOP
T9
NOP
T10
T11
Ta0
Ta1
T14
NOP
NOP
tWR^*5
PRE
VALID
NOP
NOP
TIME BREAK
TRANSITIONING DATA
DON'T CARE
Figure 47 – WRITE (BC4) OTF to PRECHARGE Operation
CK#
CK
Command^*3
T0
T1
WRITE
NOP
T2
NOP
tCCD
T3
T4
T5
NOP
WRITE
NOP
T6
NOP
T7
NOP
T8
NOP
T9
NOP
T10
T11
T12
NOP
NOP
4 clocks
NOP
T13
NOP
Address^*4
Bank
Col n
DQS, DQS#
Bank
Col b
tWPRE
tWPST
DQ^*2
WL = 5
Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din Din
n
n+1 n+2 n+3 n+4 n+5 n+6 n+7
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
WL = 5
NOTES:
1. BL8, WL = 5 (CWL = 5, AL = 0)
2. Din n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.
TRANSITIONING DATA
T14
NOP
tWR
tWTR
DON'T CARE
Figure 48 – WRITE (BL8) to WRITE (BL8)
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Publication Release Date: Jan. 20, 2015
Revision: A05