W632GU8KB Datasheet, PDF (57/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
T0
T1
CK#
CK
Command^*3
WRITE
NOP
Address^*4
Bank
Col n
tDQSS (min)
DQS, DQS#
DQ^*2
DM
T2
T3
T4
T5
T6
T7
T8
T9
T10
NOP
NOP
WL = AL + CWL
NOP
NOP
NOP
NOP
NOP
NOP
tDQSS tDSH
tWPRE(min)
tDSH
tDSH
tDSH
tWPST(min)
tDQSH(min) tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSS
tDSS
tDSS
tDSS
tDSS
Din
Din
Din
Din
Din
Din
n
n+2
n+3
n+4
n+6
n+7
NOP
tDQSS (nominal)
DQS, DQS#
DQ^*2
DM
tDQSS (max)
DQS, DQS#
DQ
DM
tWPRE(min)
tDSH
tDSH
tDSH
tDSH
tWPST(min)
tDQSH(min) tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSS
Din
n
tDSS
Din
n+2
tDSS
Din
Din
n+3
n+4
tDSS
Din
n+6
tDSS
Din
n+7
tDQSS
tWPRE(min)
tDSH
tDSH
tDSH
tDSH
tWPST(min)
tDQSH(min) tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSS
Din
n
tDSS
Din
n+2
tDSS
Din
Din
n+3
n+4
tDSS
Din
n+6
tDSS
Din
n+7
TRANSITIONING DATA
DON'T CARE
Notes:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. Din n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0 A[1:0] = 00 or MR0 A[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
Figure 40 – Write Timing Definition and Parameters
8.14.3 Write Data Mask
One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3L SDRAMs,
consistent with the implementation on DDR2 SDRAMs. It has identical timings on write operations as
the data bits as shown in Figure 40, and though used in a unidirectional manner, is internally loaded
identically to data bits to ensure matched system timing. DM is not used during read cycles, however,
DM can be used as TDQS during write cycles if enabled by the MR1[A11] setting. See section 8.3.2.7
“TDQS, TDQS#” on page 21 for more details on TDQS vs. DM operations.
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Publication Release Date: Jan. 20, 2015
Revision: A05