W632GU8KB Datasheet, PDF (100/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
10.6 DC and AC Input Measurement Levels
10.6.1 DC and AC Input Levels for Single-Ended Command and Address Signals
Table 18 – Single-Ended DC and AC Input Levels for Command and Address
PARAMETER
SYMBOL
DDR3L-1333/1600
MIN.
MAX.
DDR3L-1866
MIN.
MAX.
UNIT NOTES
DC input logic high VIH.CA(DC90) VREF + 0.09
VDD
VREF + 0.09
VDD
V
1, 5
DC input logic low
VIL.CA(DC90)
VSS
VREF - 0.09
VSS
VREF - 0.09
V
1, 6
AC input logic high VIH.CA(AC160) VREF + 0.160
Note 2
-
-
V 1, 2, 7
AC input logic low VIL.CA(AC160)
Note 2
VREF - 0.160
-
-
V 1, 2, 8
AC input logic high VIH.CA(AC135) VREF + 0.135
Note 2
VREF + 0.135
Note 2
V 1, 2, 7
AC input logic low VIL.CA(AC135)
Note 2
VREF - 0.135
Note 2
VREF - 0.135 V 1, 2, 8
AC input logic high VIH.CA(AC125)
-
-
VREF + 0.125
Note 2
V 1, 2, 7
AC input logic low VIL.CA(AC125)
-
-
Note 2
VREF - 0.125 V 1, 2, 8
Reference Voltage for
ADD, CMD inputs
VREFCA(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Notes:
1. For input only pins except RESET#. VREF = VREFCA(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 120.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ± 1% VDD (for reference: approx.
± 13.5 mV).
4. For reference: approx. VDD/2 ± 13.5 mV.
5. VIH(DC) is used as a simplified symbol for VIH.CA(DC90).
6. VIL(DC) is used as a simplified symbol for VIL.CA(DC90).
7. VIH(AC) is used as a simplified symbol for VIH.CA(AC160), VIH.CA(AC135) and VIH.CA(AC125); VIH.CA(AC160) value is used
when VREF + 0.16V is referenced, VIH.CA(AC135) value is used when VREF + 0.135V is referenced and VIH.CA(AC125) value
is used when VREF + 0.125V is referenced.
8. VIL(AC) is used as a simplified symbol for VIL.CA(AC160), VIL.CA(AC135) and VIL.CA(AC125); VIL.CA(AC160) value is used when
VREF - 0.16V is referenced, VIL.CA(AC135) value is used when VREF - 0.135V is referenced and VIL.CA(AC125) value is used
when VREF - 0.125V is referenced.
10.6.2 DC and AC Input Levels for Single-Ended Data Signals
Table 19 – Single-Ended DC and AC Input Levels for DQ and DM
PARAMETER SYMBOL
DDR3L-1333/1600
MIN.
MAX.
DDR3L-1866
MIN.
MAX.
UNIT NOTES
DC input logic high VIH.DQ(DC90) VREF + 0.09
VDD
VREF + 0.09
VDD
V
1, 5
DC input logic low VIL.DQ(DC90)
VSS
VREF - 0.09
VSS
VREF - 0.09
V
1, 6
AC input logic high VIH.DQ(AC135) VREF + 0.135
Note 2
-
-
V
1, 2, 7
AC input logic low VIL.DQ(AC135)
Note 2
VREF - 0.135
-
-
V
1, 2, 8
AC input logic high VIH.DQ(AC130)
-
-
VREF + 0.130
Note 2
V
1, 2, 7
AC input logic low VIL.DQ(AC130)
-
-
Note 2
VREF - 0.130
V
1, 2, 8
Reference Voltage
for DQ, DM inputs
VREFDQ(DC)
0.49 x VDD
0.51 x VDD
0.49 x VDD
0.51 x VDD
V
3, 4
Notes:
1. VREF = VREFDQ(DC).
2. See section 10.12 “Overshoot and Undershoot Specifications” on page 120.
3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ(DC) by more than ± 1% VDD (for reference:
approx. ± 13.5 mV).
4. For reference: approx. VDD/2 ± 13.5 mV.
5. VIH(DC) is used as a simplified symbol for VIH.DQ(DC90).
6. VIL(DC) is used as a simplified symbol for VIL.DQ(DC90).
7. VIH(AC) is used as a simplified symbol for VIH.DQ(AC135); VIH.DQ(AC135) value is used when VREF + 0.135V is referenced.
8. VIL(AC) is used as a simplified symbol for VIL.DQ(AC135); VIL.DQ(AC135) value is used when VREF - 0.135V is referenced.
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Publication Release Date: Jan. 20, 2015
Revision: A05