W632GU8KB Datasheet, PDF (25/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
8.4 No OPeration (NOP) Command
The No OPeration (NOP) command is used to instruct the selected DDR3L SDRAM to perform a NOP
(CS# LOW and RAS#, CAS#, and WE# HIGH). This prevents unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected.
8.5 Deselect Command
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR3L
SDRAM. The DDR3L SDRAM is effectively deselected. Operations already in progress are not
affected.
8.6 DLL-off Mode
DDR3L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent
operations until A0 bit is set back to “0”. The MR1 A0 bit for DLL control can be switched either during
initialization or later. Refer to section 8.8 “Input clock frequency change” on page 28.
The DLL-off Mode operations listed below are an optional feature for DDR3L. The maximum clock
frequency for DLL-off Mode is specified by the parameter tCK(DLL_OFF). There is no minimum
frequency limit besides the need to satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS
Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of
both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK), but not the Data
Strobe to Data relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller
time domain.
Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after
the Read command, the DLL-off mode tDQSCK starts (AL+CL - 1) cycles after the read command.
Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK)
and the difference between tDQSCK min and tDQSCK max is significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation is shown in the following Timing Diagram
(CL=6, BL=8):
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CK#
CK
Command
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
Bank
Col b
DQS,DQS# (DLL_on)
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
DQ (DLL_on)
DQS,DQS# (DLL_off)
RL (DLL_off) = AL + ( CL – 1 ) = 5
Dout
b
Dout
b+1
Dout
b+2
tDQSCK(DLL_off)_min
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
DQ (DLL_off)
DQS,DQS# (DLL_off)
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
tDQSCK(DLL_on)_max
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
DQ (DLL_off)
Note:
The tDQSCK is used here for DQS, DQS# and DQ to have a simplified;
the DLL_off shift will affect both timings in the same way and the skew
between all DQ, and DQS, DQS# signals will still be tDQSQ.
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
TRANSITIONING DATA
DON'T CARE
Figure 9 – DLL-off mode READ Timing Operation
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Publication Release Date: Jan. 20, 2015
Revision: A05