W632GU8KB Datasheet, PDF (104/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
VSELmax
CK or DQS
VSS or VSSQ
VSEL
time
Figure 91 – Single-ended requirement for differential signals
Note that, while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended
components of differential signals have a requirement with respect to VDD/2; this is nominally the
same. The transition of single-ended signals through the AC-levels is used to measure setup time. For
single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no
bearing on timing, but adds a restriction on the common mode characteristics of these signals.
10.6.5 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the
requirements in Table 23. The differential input cross point voltage VIX is measured from the actual
cross point of true and complement signals to the midlevel between of VDD and VSS.
VDD
CK#, DQS#
VIX
VIX
VDD/2
VIX
VSEH
Figure 92 – VIX Definition
CK, DQS
VSEL
VSS
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Publication Release Date: Jan. 20, 2015
Revision: A05