W632GU8KB Datasheet, PDF (82/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
8.19.2.3 ODT during Reads
As the DDR3L SDRAM can not terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving
the ODT pin low appropriately. RTT may not be enabled until the end of the post-amble as shown in the example below. As shown in Figure 76 below, at
cycle T15, DRAM turns on the termination when it stops driving, which is determined by tHZ. If DRAM stops driving early (i.e., tHZ is early), then tAONmin
timing may apply. If DRAM stops driving late (i.e., tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier before the
Read and enabled later after the Read than shown in this example in Figure 76.
CK#
CK
Command
Address
T0
T1
READ
NOP
VALID
ODT
RTT
DQS, DQS#
DQ
T2
NOP
T3
NOP
T4
T5
T6
NOP
NOP
NOP
ODTTLoff = CWL + AL - 2
Rtt_Nom
RL = AL + CL
T7
T8
NOP
NOP
T9
T10
T11
T12
T13
T14
T15
T16
T17
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLon = CWL + AL - 2
tAOFmin
tAOFmax
Rtt_Nom
tAONmax
Dout Dout Dout Dout Dout Dout Dout Dout
b
b+1 b+2 b+3 b+4 b+5 b+6 b+7
TRANSITIONING
Figure 76 – ODT must be disabled externally during Reads by driving ODT low.
(CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL - 2 = 8; ODTLoff = CWL + AL - 2 = 8)
DON'T CARE
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Publication Release Date: Jan. 20, 2015
Revision: A05