W632GU8KB Datasheet, PDF (41/160 Pages) Winbond – 32M X 8 BANKS X 8 BIT DDR3L SDRAM

W632GU8KB
CK#
CK
Command
T0
PREA
Ta
Tb0
Tc0
Tc1
MRS
READ^*1
READ^*1
NOP
tRP
tMOD
tCCD
Tc2
NOP
Tc3
NOP
Tc4
NOP
Tc5
NOP
Tc6
NOP
Tc7
Tc8
NOP
MRS
tMPRR
Tc9
T10
Td
NOP
NOP
tMOD
VALID
BA
3
VALID
VALID
3
A[1:0]
0
0^*2
0^*2
VALID
A[2]
1
1^*4
0^*3
0
A[9:3]
00
VALID
VALID
00
A10/AP
1
0
VALID
VALID
0
A[11]
0
VALID
VALID
0
A12/BC#
0
VALID^*1
VALID^*1
0
DQS, DQS#
DQ
RL
RL
NOTES:
1. RD with BC4 either by MRS or on the fly.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
Figure 20 – MPR Readout of pre-defined pattern, BC4, upper nibble then lower nibble
TIME BREAK
DON'T CARE
- 41 -
Publication Release Date: Jan. 20, 2015
Revision: A05