W88113C Datasheet, PDF (96/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
5.4.15 Remove Frequent SRIb & Automatic Cache Management
Control bit RMSRI (5Ch.0) should be set when entering buffer mode and be disabled in decoder_off
routine. When RMSRI (5Ch.0) is high, flag SRIb (01h.r5) is generated only by STAERR (80h.r6),
LASTBK (80h.r3) or HCEI (80h.r0).
So after the target is found and buffer-correction mode is enabled, the first interrupt is generated by
LASTBK (80h.r3) if there is no decoding error. Setting RMSRI (5Ch.0) high can reduce the overhead
of microcontroller while the automatic cache management is used.
Since the SRIb (01h.r5) interrupt is removed except for erroneous sectors, the cache management
should be implemented through TCC (9Dh). If TCINCEN (9Ch.5) is high, TCC (9Dh) increments at
the end of EDC-checking if there is no STAERR (80h.r6) or HCEI (80h.r0) error. If ACMEN (9Ch.6) is
high, TCC (9Dh) decrements at the end of each data-in block transfer. The transfer of working area
data should be implemented as linear transfer to prevent error.
Writing value to SKIPC (9Eh) can be used to implement the cache-partial-hit event. For the cache-
miss event, TCC (9Dh) should be set 0.
The stop of DSP buffering is implemented by following setting ininitialization to prevent buffer wrap-
around:
• BICCTL (9Ah) ← B0h
• BUFLIM (9Bh) ← cache_limit
The following figure shows an example flowchart under following conditions:
• Buffer-Independent-Correction is enabled
• Remove frequent SRIb is enabled in buffer mode
• Automatic transfer and cache management is enabled
• Linear address transfer for working area data is enabled
In this case, the flag TENDb (01h.r6) is generated only when the last block is transferred to host, i.e.,
TTC (9Fh) is zero.
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Publication Release Date: Mar. 1999
Revision 0.61