W88113C Datasheet, PDF (38/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
RAMWR - RAM Write Register - (write 1Eh)
To gain access to external RAM, the microprocessor should first wait for flag UTBY (1Fh.r7) to
become low, then set the address through RACLU/H/L(2Df/1Dh/1Ch).
Writing data into register RAMWR triggers the following sequence:
• Data is transferred from the microprocessor to register RAMWR.
• Data is transferred from RAMWR to the RAM located by the address counter.
• Increments RACL, RACH, and RACU increments by one
• Clear flag UTBY
RAMRD - RAM Read Register - (read 1Eh)
To gain access to external RAM, the microprocessor should first wait for flag UTBY (1Fh.r7) to
become low, then set the address through RACLU/H/L (2Df/1Dh/1Ch).
Writing data into register RAMRD triggers the following sequence:
• Data previously stored in RAMRD is transferred to the microprocessor.
• RAM data located by the address counter is transferred to the RAMRD register.
• Increments RACL, RACH, and RACU increments by one
• Clear flag UTBY
Note that the first data read from RAMRD is invalid.
HICTL0 - Host Interface Control Register - (write 1Fh)
Bit 7-6: reserved
Bit 5: H16S - (obsolete)
No matter what value is set, the data transfer between host and decoder is using 16-bit
protocol.
Bit 4: LAEN - Latch Enable
If this bit is high, host address and chip-select signals will be latched when pins HRDb or
HWRb change from high to low.
Bit 3: MDMA - Multi-word DMA mode
Setting this bit to high enables multi-word DMA mode if PIO (1Fh.2) is low.
Bit 2: PIO - PIO/DMA mode select
Setting this bit high causes data transfer to/from host using PIO mode. This bit is also
controlled by bit-0 of ATFEA (1F1h/171h) if ASMDA (5Bh.7) is high.
Bit 1: DINB - Data-In Transfer Enable
Setting this bit low select data-in transfer. Otherwise, the data-out transfer is enabled.
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Publication Release Date: Mar. 1999
Revision 0.61