W88113C Datasheet, PDF (83/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
• set TWCH/L (03h/02h) as 008Fh
• set TACH/L (05h/04h) as 0800h
Case 3: The 2352 bytes of sync, header, user data and EDC&ECC are request by host.
• set TBH/L (25h/24h) as 001Fh
• set TWCH/L (03h/02h) as 0497h
• set TACH/L (05h/04h) as FFF0h
If the requested data is not stored continuously in DRAM, e.g., header and EDC&ECC data, more than one
transfer has to be triggered.
5.1.4 16-bit DRAM
High DRAM bandwidth is the key issue to support high disk speed and can be dramatically by using
16-bit DRAM.
The following setting should be made at initialization to utilize 16-bit DRAM.
• The control bit ALE2 (5Ch.3) should be set high (default after chip reset).
• The value of RTC2-0 (2Ah.2-0,w) should be 101b (9 col) or 100b (8 col).
• The Ring Control Registers (50h-57h) should also be set to fully utilize the DRAM space.
Since DRAM access is based on linear addressing, there is no need of further firmware change.
5.1.5 EDO DRAM
EDO DRAM is designed to improve the DRAM read performance. The EDO DRAM support is
enabled by setting control bit EDOEN (88h.w0) high. When this bit is set high, the data latch timing
of DRAM changes to falling edge instead of rising edge of internal clock.
The timing of DRAM is controlled by MRCD (88h.w5) and FRCDb (88h.w1). The slower timing may
be required to support some slower DRAMs.
MRCD FRCDB
tRCD
tRP
tPC
Minimum Cycle
0
0
1T
1.5 T
1T
3T
0
1
2T
1.5 T
1T
4T
1
0
1.5 T
1T
1T
3T
1
1
x
x
x
x
Note: T is the system clock period.
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Publication Release Date: Mar. 1999
Revision 0.61