W88113C Datasheet, PDF (32/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 3: CPFT - Clear Packet FIFO Trigger
Setting this bit high clears the Packet FIFO.
Bit 2: ADTT - Automatic Data Transfer Trigger
If PIO (1Fh.2) is high, setting ADTT high triggers the following PIO Data Transfer sequence:
• Set BSY
• DTEN (01h.w2) ← 1
• SCoD (20h.2) ← 0 if DINB (1Fh.1) is 0; otherwise, 1
• ATINT (32h) ← 02h if DINB (1Fh.1) is 0; otherwise, 00h
• If STWCEN (18h.w3) is enabled, then ATBHI/LO ← (TWCH/L + 1) × 2
The data transfer logic will start to fill the Data FIFO automatically. The following sequence
will be executed when DFRDYb (01h.r1) become active-low:
• DRQ (37h.3) ← 1
• Clear BSY
• HIRQ (2Eh.3) ← 1
After detecting the interrupt, the host will check the status and then read the data.
STWCEN (18h.3) should not be used for Automatic Multiple Block Transfer. Instead, ATBLO,
ATBHI should be set by firmware to: (MBC + 1) × ((TWC + 1) × 2)
If PIO (1Fh.2) is low, setting ADRTG high triggers the following DMA Data Read sequence:
• Set BSY
• DTEN (01h.w1) ← 1
• SCoD (20h.2) ← 0 if DINB (1Fh.1) is 0; otherwise, 1
• ATINT (32h) ← 02h if DINB (1Fh.1) is 0; otherwise, 00h
Bit 1: DRQT - DRQ Trigger
If bit PIO (1Fh.2) is high, setting this bit high triggers the following hardware sequence:
• DRQ (37h.3) ← 1
• BSY ← 0
• HIRQ (2Eh.3) ← 1
When bit PIO is low (DMA mode), this bit should not be triggered.
Bit 0: SCT - Status Completion Trigger
Setting this bit high triggers the following hardware sequence:
• CHECK (37h.0) ← ACHECK (3Eh.0)
• CORR (37h.2) ← ACORR (3Eh.2)
• DRDY (37h.6) ← ADRDY (3EH.6)
• ATINT (32h) ← 03h
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Publication Release Date: Mar. 1999
Revision 0.61