W88113C Datasheet, PDF (35/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 2: AUCRCEN - Automatic Ultra DMA CRC Error Logic Enable
If AUCRCEN (18h.2) is set high, the automatic status complete logic would be stopped if
UCRCOKB (30h.r3) is high. If no CRC error has occurred in last Ultra DMA burst, status
complete sequence would be automatically executed. This bit should be set high only if
ASCEN (18h.5) is set high as well. This bit is automatically clear when: (1) automatic status
complete sequence is triggered or (2) SCT (17h.w0) is set high.
Bit 1: ABYEN - Automatic BSY Set Enable
When this bit is high, the following sequence is executed when Disk Seek Complete is
triggered by DSCT (17h.w5):
• Set BSY
• DSC (37h.4) ← 1
• Clear BSY
• DSCT ← 0
Bit 0: A0IEN - A0h Command Interrupt Enable
If this bit is high and APKTEN (18h.7) has been enabled, HIRQ (2Eh.3) becomes active-high
after an opcode A0h is issued to ATA Command Register.
CCTL0 - Clock Control Register 0 - (write 19h)
This register is 0 after chip reset.
Bit 7: CKSTP - Clock Stop
Setting his bit high stops the internal clock and the clock output at pin CLKO. CKSTP is de-
activated by the following events:
• Chip reset or host reset or firmware reset
• Command write from the host while the drive is selected
• Host issues Diagnostic Command, regardless of drive selection
• Host issues command to shadow drive if SHDRV (3Fh.6) is enabled
• Host set bit SRST in ATAPI Device Control Register high, regardless of drive selection
Bit 6: reserved
Bit 5: JPSS - Jumper Sampling Select
This bit is used to control the sampling of pin RD15/DJ. When JPSS is high, pin RD15/DJ is
sampled while chip reset is active. When this bit is low, PAR/JP is sampled while chip reset
or host reset are active.
Bit 4: Reserved
Bit 3-0: CKS[3:0] - Clock Skew Control
CKS3-0 are used to control the duty cycle of the internal clock. The low period of cycle
increases as the skew value increments.
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Publication Release Date: Mar. 1999
Revision 0.61