W88113C Datasheet, PDF (49/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 4: SHDC - Shadow Command Flag
This bit becomes high when the host writes a command to a non-existent slave drive.
Meanwhile, pin UINTb (36) becomes low-active if SHIEN (2Eh.w2) is enabled. ATAC is de-
activated by the following:
• Chip reset or host reset
• Reading register ATCMD (37h)
• Writing 1 to CLRBSY (20h.4)
Bit 3: ARST - ATAPI Soft Reset Flag
This bit becomes high when ATAPI Soft Reset command (opcode 08h) is written to either
master or slave drive. ARST is de-activated by writing any value to register ARSTACK
(30h,w).
Bit 2: RST - Reset Flag
This bit is high when the chip is currently being reset by chip reset, host reset, or firmware
reset.
Bit 1: FRST - Firmware Reset Flag
This bit is high if the current or most recent reset was firmware reset. The first read of
register MISS1 (2Fh,r) following the end of the firmware reset clears this flag to 0.
Bit 0: HRST - Chip reset or host reset Flag
This bit is high if the current or most recent reset was activated by chip reset or host reset.
The BSY flag is set whenever chip reset or host reset is activated. The first read of register
MISS1 (2Fh,r) following the end of the chip reset or host reset clears this flag to 0.
ARSTACK - ATAPI Soft Reset Acknowledge (write 30h)
Writing any value to this register triggers the following events:
• Clears ARST (2Fh.r3)
• Deactivates pin ARSTb if ARSTS1-0 (2Fh.w3-2) is 3
• Deactivates pin UINTb if ARSTIEN (2Fh.w1) is enabled
MISS2 - Miscellaneous Status Register 0 (read 30h)
Bit 7: SRSTD - Soft Reset with DRQ
This bit becomes high if host activates SRST in the ATAPI Device Control Register while
DRQ is high and the drive is selected. This bit is updated at rising edge of SRST.
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Publication Release Date: Mar. 1999
Revision 0.61