W88113C Datasheet, PDF (63/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 3: SBCK - Select BCK as subcode clock
When this bit is high, the pin BCK (10) is selected as subcode reference clock instead of
system clock. This setting is suitable for drive using CAV subcode.
Bit 2: CAS8B - Eight CAS in One RAS Enable
When this bit is set low, maximum the number of Column Address Strobe is 8 instead of 4 in
one DRAM FPM cycle.
Bit 1: FRCDB - Fast RAS to CAS Delay
The bit controls the timing of tRCD and tRP.
Bit 0: EDOEN - EDO DRAM Support Enable
Setting this bit enables EDO DRAM support and the data latch timing of DRAM changes to
falling edge instead of rising edge of internal clock.
DRAM Timing Setting
The timing of DRAM is controlled by MRCD (88h.5) and FRCDb (88h.1). The slower timing
may be required to support some slower DRAMs.
MRCD FRCDB
tRCD
tRP
tPC
Minimum Cycle
0
0
1T
1.5 T
1T
3T
0
1
2T
1.5 T
1T
4T
1
0
1.5 T
1T
1T
3T
1
1
x
x
x
x
Where T is the system clock period.
tRP
tRAS
RASB
tRCD
tPC
CASB
DRAM Timing
- 59 -
Publication Release Date: Mar. 1999
Revision 0.61