W88113C Datasheet, PDF (72/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
ACCTL - Automatic Cache Control Register - (read/write 9Ch)
This register is 0 after chip reset, host reset and firmware reset.
Bit 7: ATTEN - Automatic Transfer Trigger Enable
The control bit ADTT (17h.w2) is automatically set high if all the following conditions are met:
• ATTEN (9Ch.7) is high
• TCC (9Dh) is not zero
• TTC (9Fh) is not zero
Bit 6: ACMEN - Automatic Cache Management Enable
If ACMEN (9Ch.6) is high, the following functions are enabled:
• TBKH/L (25h/24h) increments at the end of each data-in block transfer
• TCC (9Dh) and TTC (9Fh) decrements at the end of each data-in block transfer
• TCC (9Dh) minus N and TBKH/L (25h/24h) plus N right after SKIPC (9Eh) is set N
If ACMEN (9Ch.6) is high and TTC (9Fh) is not zero, the following functions are executed
when ADTT (17h.w2) is triggered:
• MBC4-0 (12h.4-0) ← min{ ATLIM (9Ch.4-0), TCC (9Dh), TTC (9Fh) } minus 1
• ATBHI/LO (35h/34h) ← (MBC4-0 + 1) × (TWCH/L + 1) x 2 if STWCEN (18h.3) is high
Registers SKIPC (9Eh) and TTC (9Fh) are stuck at 0 if ACMEN (9Ch.6) is low.
Bit 5: TCINCEN - Transfer Cache Increment Enable
When this bit is high, the TCC (9Dh) increments at the end of EDC-checking if there is no
STAERR (80h.r6) or HCEI (80h.r0) error. This bit should be high if TCC (9Dh) is used to
implement cache management.
Bit 4-0: ATLIM[4:0] - Automatic Transfer Block Limit
If ACMEN (9Ch.6) is high and TCC (9Fh) is not zero, these five bits specify the maximum
number of blocks that can be transferred to host in one trigger. The minimum limit is 1.
Setting 0 to these bits specify limit as 32 blocks.
TCC - Transfer Cache Counter - (read/write 9Dh)
This counter can be used to implement cache management if RMSRI (5Ch.0) is high. If TCINCEN
(9Ch.5) is high, TCC (9Dh) increments at the end of EDC-checking if there is no STAERR (80h.r6) or
HCEI (80h.r0) error. If ACMEN (9Ch.6) is high, TCC (9Dh) decrements at the end of each data-in
block transfer unless the value is zero. The value follows 0 is 0. The transfer of working area data
should be implemented as linear transfer to prevent extra decrement of this counter.
If ACMEN (9Ch.6) is high, TCC (9Dh) minus N right after SKIPC (9Eh) is set N. This function can be
used to implement the cache-partial-hit event.
This register is 0 after chip reset, host reset and firmware reset. This counter should be set 0 in
cache-miss case. Writing this register should be prevented when the decoder is on or the data-in
transfer is in progress.
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Publication Release Date: Mar. 1999
Revision 0.61