W88113C Datasheet, PDF (29/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
MBTC0 - Multi-Block Transfer Control 0 - (read/write 12h)
The host interface supports multi-block transfer without microprocessor intervention by following
sequence:
• MBC (12h.4-0) ← the number of block to be transferred minus 1 (ex. 3)
• TWCH/L (03h/-2h) ← the number of words to be transferred in each block minus 1 (ex.
1175)
• TACH/L (05h/04h) ← the starting point of the block (ex. F4h, FFh)
• TBH/L (25h/24h) ← the RAM block number of the first block to be transferred (ex. 5)
• ATBHI/LO (35h/34h) ← the total bytes to be transferred (ex. 9408)
• ADTT (17h.w4) ← 1
PS: STWCEN (18h.3) should not be set in multi-block transfer operation.
When ADTT is set, host will receive HIRQ, check status, and then start to read data.
After the last word of one block (except the last one) is read by the host, the following hardware
sequence is executed:
• TWCH/L (03h/02h) ← reload
• TACH/L (05h/04h) ← reload
• TBH/L (25h/24h) ← auto-increment
• MBC0 (12h.4-0) ← auto-decrement
Flag TENDb (01h.r6) only becomes active at the end of data transfer of the last block. This register is
0 after chip reset, host reset and firmware reset.
HIRQ
<Multi-Block Transfer Flow Example>
TENDb(01h.r6)
data transfer
transfer trigger
N
N+1
status complete
N+2
N+3
MBC(12h.4-0)
3
2
1
0
TBH/L(25h/24)
5
6
7
8
TWC/TAC
reload
TWC/TAC
reload
TWC/TAC
reload
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Publication Release Date: Mar. 1999
Revision 0.61