W88113C Datasheet, PDF (65/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 5-4: UDT[1:0] - Ultra DMA Timing Control
These two bits define the Ultra DMA Timing Factor, udtf, which control the timing of Ultra
DMA transfer.
Tcyc = ( 2 + udtf ) × Tudma
where Tudma is clock period that depends on setting of UCLKS (8Ah.3)
and Tcyc is Ultra DMA cycle time (from DSTROBE edge to DSTROBE edge)
Device firmware should set udtf according to the clock source and the assigned Ultra DMA
transfer mode after host issues SET FEATURE command. If there are frequent CRC errors
in data-in bursts, device firmware may switch system to slower Ultra DMA mode by
increasing udtf to improve data integrity.
Example: If UCLKS (8Ah.3) is low and system clock is 33.8688MHz, the udtf should be the
following value to abide by the determined Ultra DMA mode.
Ultra DMA
Tcyc Min. Spec.
Tcyc
udtf
Mode 0
114 ns
118 ns
2
Mode 1
75 ns
88.6 ns
1
Mode 2
55 ns
59 ns
0
Bit 3: UCLKS - Ultra DMA Clock Select
If this bit is high, the clock source for UDMA is from pin ACLK (46). If this bit is low, the clock
source is system clock.
Bit 2-0: REFT[2:0] - Refresh Timing Control
The frequency of refresh is controlled by REFT2-0 (8Ah.2-0) to support long refresh. The
value after chip reset is 0. The refresh cycle defaults to be issued once after 256 system
clocks.
refresh period = 256 × 2reft system clock periods
STA0M - Status 0 Mask Register - (write 8Ch)
If any following bit is enabled, the flag STAERR (80h.r6) becomes high when the corresponding
status bit becomes active.
Bit 7 - CRCOK Mask
Bit 6 - ILSYNC Mask
Bit 5 - NOSYNC Mask
Bit 4 - LBLK Mask
Bit 3 - WSHORT Mask
Bit 2 - SBLK Mask
Bit 1 - BIN0 Mask
Bit 0 - UCEBLK Mask
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Publication Release Date: Mar. 1999
Revision 0.61