W88113C Datasheet, PDF (88/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
of registers TWCH/L (03h/02h) should be set 4 instead of 5. Then firmware should repeatedly read
register PFAR (00h,r) after Transfer End Interrupt asserts until flag PFNEb (01h.r7) becomes one.
<example> data-out transfer sequence:
1. TENDEN (01h.w6) ← 1
2. ASCTRL (18h,w) ← 58h
3. HICTL0 (1Fh.w) ← 0Bh
// UDMA data-out
4. TWC (03h/02h,w) ← min(0004h, byte_cnt/2-1)
5. ADTT (17h.w2) ← 1
// automatic data transfer trigger
6. wait TENDb (01h.r6) = 0 and TDIR (30h.r5) = 1 and FPKT (30h.r1) = 1
7. TACK (07h,w) ← FFh
8. read PFAR (00h,r); byte_cnt =byte_cnt - 1
9. if PFNEb (01h.r7) is low, repeat step (8)
10.if (byte_cnt ≠ 0) goto step (4)
11.SCT (17h.0) ← 1
// status complete trigger
5.3.3 Ultra DMA Error Handling
Flag UCRCOKb (30h.r3) is used to determine if a CRC error event has occurred during latest Ultra
DMA burst. If AUCRCEN (18h.2) and ASCEN (18h.5) are both set high, the automatic status
complete logic would not be triggered if UCRCOKb (30h.r3) is high. Therefore, firmware should
check UCRCOKb (30h.r3) flag after each Ultra DMA burst. If a CRC error has occurred, firmware
should set CHK (37h.0) to one and manually trigger status complete.
5.3.4 Ultra DMA Data-In Transfer Diagram
DMARQ(53)
DMACKb(48)
HRDb(50)
HWRb(52)
IORDY(49)
DFRDYb(01h.1)
TENDb(01h.6)
FIFO prefetch
commdnad
Data transfer trigger
UDMA Burst
Tcyc
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Publication Release Date: Mar. 1999
Revision 0.61