W88113C Datasheet, PDF (22/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
EIAL/EIAH - ECC Initial Address - (read 08h/09h, write 0Ch/0Dh)
EIAH/L are used to hold the initial address offset of the data block to be corrected. The content of
BIAH/L (09h/08h,w) will be automatically loaded to EIAH/L at the beginning of each data sync,
making it unnecessary to read or write EIAH/L during normal operation. The RAM block for ECC is
controlled by the number in registers DDBH/L (29h/28h).
CTRL0 - Control Register 0 - (write 0Ah)
This register is 0 after chip reset, host reset, firmware reset and decoder reset.
Bit 7: DECEN - Decoding Logic Enable
Setting this bit high enables the decoding logic.
Bit 6: RTEDC - Real Time EDC Checking Enable
Setting this bit high enables the real-time-EDC-checking logic. The RSPC error correction is
performed only when the result of real time EDC check is error. This function could save
about 2/3 of DRAM bandwidth compared with conventional decoder.
Bit 5: EDCEN - Error Detect and Correct Enable
Setting this bit high enables the ECC and EDC logic. Change of this bit takes effect after next
sync.
Bit 4: ACEN - Automatic Correction Enable
If both M2RQ (0Bh.w3) and this bit is high, the type of error correction is automatically
determined by FORM bit in the subheader byte. If only M2RQ (0Bh.w3) is high, the type of
error correction is controlled by F2RQ (0Bh.w2). If M2RQ (0Bh.w3) is low, this bit does not
affect the correction of mode 1 data.
Bit 3: PKTINH - obsolete
Bit 2: BUFEN - Buffering Enable
Setting this bit high enables incoming DSP data buffering. When this bit is high, the values
of register HEAD0-3(04h-07h) and SUBH0-3(14h-17h) are retrieved from external RAM rather
than from incoming serial data. When BUFEN is low, any setting of QCEN or PCEN is
meaningless. Change of this bit takes effect after next sync.
Bit 1: QCEN - Q-codeword Correction Enable
When this bit is high, Q-codeword RSPC correction logic is enabled. Change of this bit takes
effect after next sync.
Bit 0: PCEN - P-codeword Correction Enable
When this bit is high, P-codeword RSPC correction logic is enabled. Change of this bit takes
effect after next sync.
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Publication Release Date: Mar. 1999
Revision 0.61