W88113C Datasheet, PDF (71/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
BICCTL - Buffer Independent Correction Control Register - (read/write 9Ah)
This register is 0 after chip reset, host reset and firmware reset.
Bit 7: BICEN - Buffer Independent Correction Enable
If this bit is high, the buffer-independent-correction (BIC mode) is enabled. Otherwise, the
real-time-correction (RTC mode) is enabled.
Bit 6: ATMSEN - Automatic Mode Switch
If this bit is high, the decoder automatically change from Disk-Monitor Mode to the pre-set
Buffer-Mode after the target is found.
Bit 5: BLIMEN - Buffer Limit Enable
If BLIMEN (9Ah.5) is high, the buffering of DSP data stops when the condition defined by
BLIMS (9Ah.4) is met. This function should be enabled if BICEN (9Ah.7) is set high.
Bit 4: BLIMS - Buffer Limit Source Select
If BLIMS (9Ah.4) is high, the buffering stop when BUFC (9Bh,r) reach BUFLIM (9Bh,w). If
BLIMS (9Ah.4) is low, the buffering stop when buffering block (internal) reach TBH/L
(24h/25h,r) minus 1.
Bit 3-0: RCLIM[3:0] - Repeat Correction Limit
If BICEN (9Ah.7) is high, these four bits specify the maximum number of repeat correction.
BUFLIM - Buffer Limit Register - (write 9Bh)
This register is used as buffer limit when BLIMS (9Ah.4) is high. If BUFCWEN (92h.w4) is low, this
register can be set the buffer-ring size minus n, where n is larger than 1. This register is 0 after chip
reset, host reset and firmware reset. In normal operation, this register only needs to be set once after
power-on.
BUFC - Buffer Counter - (read 9Bh)
This counter increments when a sector is buffered into external RAM. If ACMEN (9Ch.6) is high,
BUFC (9Bh,r) decrements at the end of each data-in block transfer unless the value is zero. The
value follows 0 is 0. The transfer of working area data should be implemented as linear transfer to
prevent extra decrement of this counter.
If ACMEN (9Ch.6) is high, BUFC (9Bh,r) minus N right after SKIPC (9Eh) is set N. This function can
be used to implement the cache-partial-hit event.
If both BLIMEN (9Ah.5) and BLIMS (9Ah.4) is high, the buffering stop when this count reaches
BUFLIM (9Bh,w). The value in BUFC (9Bh,r) may exceed BUFLIM (9Bh,w) by one.
This counter is synchronized to TCC (9Dh) whenever DECEN (0Ah.w7) is low.
This counter is 0 after chip reset, host reset and firmware reset.
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Publication Release Date: Mar. 1999
Revision 0.61