W88113C Datasheet, PDF (64/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
DFFCNTL - Data FIFO Threshold Control Register - (read/write 89h)
Bit 7,6: Reserved
Bit 5-3: DFFHT[2:0] - Data FIFO High Threshold
When the number of bytes in Data FIFO larger than DFFHT, device stops pre-fetch to
prevent FIFO overrun. Since the default setting of CAS8B (88h.2) is low, the default value of
DFFHT is 001b.
DFFHT[2:0] Threshold
000b
28
001b
24
default
011b
16
Bit 2-0: DFFLT[2:0] - Data FIFO Low Threshold
When the number of bytes in Data FIFO less than DFFLT, device de-activates DMARQ to
prevent FIFO underrun in traditional DMA mode. When the number of bytes in Data FIFO
less than DFFLT, device would stop issuing DSTROBE to prevent FIFO underrun in Ultra
DMA data-in mode.
DFFLT[2:0]
Threshold
000b
4
default
001b
8
011b
16
ATCTL - Auxiliary Timing Control Register - (read/write 8Ah)
This register is set 00h after chip reset, host reset and firmware reset.
Bit 7: XOFF - Crystal Off
Setting his bit high can turn off the crystal cell and save power consumption. XOFF is de-
activated by the following events:
• Chip reset or host reset or firmware reset
• Command write from the host while the drive is selected
• Host issues Diagnostic Command, regardless of drive selection
• Host issues command to shadow drive if SHDRV (3Fh.6) is enabled
• Host set bit SRST in ATAPI Device Control Register high, regardless of drive selection
Bit 6: reserved.
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Publication Release Date: Mar. 1999
Revision 0.61