W88113C Datasheet, PDF (47/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 5-4: HRSTS[1:0] - HRSTb Pin Function Select
HSTS[1] HSTS[0]
type
function of pin 21
remark
0
0
I/OD
GIO1
default
0
1
O
DA1
1
0
I
HRSTb
1
1
I
HRSTb
Bit 3-2: ARSTS[1:0] - ARSTb Pin Function Select
ARSTS[1] ARSTS[0] type
function of pin 60
remark
0
0
I/OD
GIO2
default
0
1
O
DA2
1
0
OD
ARSTb (reset-mode)
1
1
OD
ARSTb (interrupt-mode)
When ARSTS1 is high, pin ARSTb (60) becomes active-low if host writes an ATAPI Soft
Reset Command. In interrupt-mode, writing any value to register ARSTACK (30h,w) de-
activates pin ARSTb (60). In reset-mode, pin ARSTb (60) automatically de-activates itself
after 256 system clock.
Bit 1: ARSTIEN - ATAPI Soft Reset Interrupt Enable
When this bit is high, pin UINTb (36) becomes active-low whenever host writes an ATAPI Soft
Reset Command (opcode is 08h).
Bit 0: ARWC - ATAPI Register Write Control
Host writes to ATAPI registers (except Device Control Register) will not take effect when
ARWC and BSY are high, if BSY is not set by the following commands:
• Opcode 90h is written to ATA Command Register while the drive is selected.
• Opcode 90h is written to ATA Command Register while the shadow drive is selected if
SHDRV (3Fh.6) if high.
MISS1 - Miscellaneous Status Register 0 - (read 2Fh)
Bit 7: SRST - Soft Reset Flag
This bit becomes high when host writes 1 to bit SRST in the ATAPI Device Control Register if
either master or slave drive is selected. When SRST becomes high, the following events will
be executed:
• BSY (37h.7) ← 1
• Initialize ATAPI signature
• PDIAGEN (20h.w6) ← 0 and disables pin PDIAGb (43) to high-impedance state
- 43 -
Publication Release Date: Mar. 1999
Revision 0.61