W88113C Datasheet, PDF (56/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
PSKCTL - Programmable System Clock Control Register - (read/write 59h)
This register should be set before the programmable system clock is enabled by setting PSKEN
(1Ah.w4) high. This register is 0 after chip reset.
Bit 7: PSKSEL (write) - Programmable System Clock Select
If this bit is high, the internal system clock will be adjusted to fit the programmed frequency
according Crystal input. If this bit is low, the internal system clock will be adjusted to fit the
programmed frequency according to internal clock.
Bit 7: LOCKED (read) - Programmable System Clock Locked
This bit is high once the internal system clock is ever on lock with the programmed frequency.
Bit 6: LOCKSEL (write) - Programmable System Clock Lock Select
If this bit is high, the internal system clock will keep the same delay path once the
programmed frequency is locked. This function keeps system clock at steady frequency, but
the frequency may be affected by temperature. If this bit is low, the internal system clock will
be continuously adjusted to fit the programmed frequency according to Crystal input and
result in a various frequency.
Bit 6: ONLOCK (read) - Programmable System Clock On Lock
This bit is high if internal system clock is on lock with the programmed frequency.
Bit 5-0: PSK[5:0] - Programmable System Clock Factor
If PSKEN (1Ah.w4) and PSKSEL (59h.w7) are high, these six bits are used to controlled the
internal system frequency. The equation is:
frequency system clock = frequency of XIN × (PSK[5:0] + 2) ÷ 16
SCTC - Subcode Timer Control Register - (write 5Ah)
If SBXCK (2Ch.w7) and CD2SC (2Ch.w5) are both low, the clock used by subcode logic clock is
controlled by SUBCS2-0 (21h.w2-0) unless any non-zero value is written into this register. The value
of this register should be calculated as follows:
( N + 2 ) × tc × dsf = 11.3 / 2
where tc is the internal clock period(ex: 50nS for 20MHz crystal),
dsf is the disk speed factor(ex: 4 for 4-fold speed drive).
There is no need to set this register if SBCK (88h.w3) is set high.
EFCTL - Enhanced Feature Control Register - (read/write 5Bh)
Bit 7: ASDMA - Automatic Set DMA
If this bit is high, the inverted value of DMA bit of ATFEA (1F1h,w) will be automatically
loaded to PIO (1Fh.2). This bit is 0 after chip reset, host reset and firmware reset.
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Publication Release Date: Mar. 1999
Revision 0.61