W88113C Datasheet, PDF (85/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
5.2.2 General I/O
Pin HRSTb (21) and pin ARSTb (60) can be configured as general I/O pins through register MISC1
(2Fh,w). The state of these two general I/O pins can be controlled through register GIOCTL (5Fh).
The pin state of URS (32) can be read back from GIN3 (5Fh.r2) if DRA (5Bh.1) is high and DA0EN
(87h.7) is low.
5.2.3 Programmable System Clock
The internal system frequency is controlled by CCTL1 (1Ah,w) and PSKCTL (59h,w). Register
PSKCTL (59h,w) should be set before the programmable system clock is enabled by setting PSKEN
(1Ah.w4) high. If both PSKEN (1Ah.w4) and PSKSEL (59h.w7) are high, PSK5-0 (59h.5-0) are used
to controlled the internal system frequency. Register PSKCTL (59h,w) should be set before the
programmable system clock is enabled by setting PSKEN (1Ah.w4) high. The equation is:
frequency system clock = frequency of XIN × (PSK[5:0] + 2) ÷ 16
The variation of the resultant system frequency is normally less than 5%.
<example> If the frequency of pin XIN (15) is 33.8688 MHz, PSKEN (1Ah.w4) and PSKSEL (59h.w7)
are high:
PSK5-0
System Frequency
0Fh
36 MHz
11h
40.2 MHz
13h
44.4 MHz
15h
48.7 MHz
17h
53 MHz
19h
57.2 MHz
1Bh
61.4 MHz
<example> If the frequency of pin XIN (15) is 24 MHz, PSKEN (1Ah.w4) and PSKSEL (59h.w7) are
high:
PSK5-0
System Frequency
14h
33 MHz
16h
36 MHz
18h
39 MHz
1Ah
42 MHz
1Ch
45 MHz
1Eh
48 MHz
20h
51 MHz
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Publication Release Date: Mar. 1999
Revision 0.61