W88113C Datasheet, PDF (58/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
Bit 1: reserved
Bit 0: RMSRI - Remove Frequent SRIb
If RMSRI (5Ch.0) is high, flag SRIb (01h.r5) is generated only by flags STAERR (80h.r6),
DSFULI (80h.r4), LASTBK (80h.r3), LTTI (80h.r2), TNFI (80h.r1) or HCEI (80h.r0). Setting
this bit high can reduce the overhead of microcontroller while the automatic cache
management is used. This bit is 0 after chip reset, host reset and firmware reset.
LSUBH2 - Latched Subheader 2 Register - (read 5Dh)
The content of Subheader-2-Register(16h) is latched into this register at the end of EDC check. This
value is available to the end of next EDC check.
PSKCNT - Programmable System Clock Internal Counter (read 5Eh)
Bit 4-0 of this register hold the internal counter of programmable clock system. This value can be
read for ststem debug.
GIOCTL - General I/O Port Control Register - (read/write 5Fh)
Pin HRSTb (21) can be configured as GIO1 by HRSTS1-0 (2Fh.5-4). Pin ARSTb (60) can be
configured as GIO2 by ARSTS1-0 (2Fh.3-2). This register is 0 after chip reset.
Bit 7-6: reserved
Bit 5: G2OEN - General I/O Port 2 Output Enable
Setting this bit high configure GIO2 as output. Otherwise, it is an input pin.
Bit 4: G1OEN - General I/O Port 1 Output Enable
Setting this bit high configure GIO1 as output. Otherwise, it is an input pin.
Bit 3: reserved
Bit 2: GIN3 - General Input Port 3
The pin state of URS (32) can be read back from this bit if DRA (5Bh.1) is high and DA0EN
(87h.7) is low.
Bit 1: GIO2 - General I/O Port 2
If GIO2 is configured as an input pin, the pin state can be read back from this bit. If GIO2 is
configured as an output pin, set this bit low drive GIO2 low and set this bit high cause a weak
pull-up.
Bit 0: GIO1 - General I/O Port 1
If GIO1 is configured as an input pin, the pin state can be read back from this bit. If GIO1 is
configured as an output pin, set this bit low drive GIO1 low and set this bit high cause a weak
pull-up.
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Publication Release Date: Mar. 1999
Revision 0.61