W88113C Datasheet, PDF (20/102 Pages) Winbond – ATAPI CD-ROM DECODER & CONTROLLER

W88113C
TWCL - Transfer Word Counter Low- (read/write 02h)
Before triggering data transfer, the number of words to be transferred should be set through 12-bit
Transfer Word Counter (TWC). The number of words minus 1 should be written to this counter while
using standard ATAPI 16-bit data transfer. After host read one word, the counter is decreased by
one. Transfer End Interrupt Flag, TENDb (01h.r6), is activated when this counter becomes zero.
Bit 7-0: TWCH[7:0] - Transfer Word Count Low
TWCH - Transfer Word Counter High - (read/write 03h)
Bit 7: LATXF - Linear Address Transfer Enable
If this bit is high, the Linear Address Transfer is enabled. In this case, the data stored from
the address specified by RAC (2Dh,1Dh,1Ch) are transferred to host after trigger. The size of
transfer data is limited by TWC (03h/02h). Setting this bit high cause UTBY (1Fh.r7) high to
inhibit uP to access RAMRD (1Eh,r) or RAMWR (1Eh,w).
If this bit is low, the Block-Offset Transfer is enabled. In this case, the data stored from the
address specified by TBH/L (25h/24h) and TACH/L (05h/04h) are transferred to host after
trigger. The address of data warps around at the block boundary, so the size of transfer data
is limited by block size.
Bit 3-0: TWCH[3:0] - Transfer Word Count High
TACL/TACH - Transfer Address Counter - (write 04h/05h)
Before triggering block-offset data transfer, the external RAM address of data to be transferred should
be set through TACH/L (05h/04h,w). This number in this counter specifies the first available data
address relative to the beginning of the block. The block number should also be specified through
Transfer Block registers TBH/L (25h/24h). After one word is read by host, TACH/L are incremented to
the next available data address. The following equation illustrates the relation between block-offset
and linear address:
linear address = (block number × block size) + address offset
THTRG - Transfer to Host Trigger Register - (write 06h)
This register is used to trigger data transfer regardless of what value is written. If DINB (1Fh.1) is low,
triggering this register automatically fills the Data FIFO and then flag DFRDYb (01h.r1) becomes
active-low when the Data FIFO becomes ready. If DINB (1Fh.1) is high, data-out transfer is enabled,
e.g., parameter of mode-select command. A more convenient way is set ADTT (17h.w2) high and
then trigger hardware data transfer sequence.
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Publication Release Date: Mar. 1999
Revision 0.61